1. Field of Invention
Design For Yield (DFY) is design to increase the yield in the real production chip. In the real chip, it is very complicated system. On the chip, there is a lot of noise. The circuit is not only designed for the silent solid power and ground but also has to work in the dynamic noisy environment.
Before, we have a large board, small chips and low ramping signal in the slow signal process. We can assume solid power and ground on the board and all the noise is dumped onto the board. Now, we have a tiny board, the giant SOC chips and the fast rising and falling signal in the signal process. We can no more assume the solid power and ground on the board and have all the noise been dumped onto the board. The chip and board are very noisy. However, today's analog front end (AFE) design is sill based on the “implicit assumptions” of the old-time design style. The AFE have very poor performance in such a noisy environment. The traditional AFE design is the army style circuit design. The earth is solid and not moving. Today analog circuit on SOC chip is the navy style circuit. The sea oscillates and vibrates violently. So, all the AFE sub-modules work individually. However, as they are put together on the SOC chip, the analog circuit does not work properly. The board is very noisy. All the digital noise is leaked to the tiny board.
The original definition of mixed signal simulation=analog (SPICE)+digital (Verilog). However, the mixed signal analog circuit has to survive in the noisy SOC environment. So, based on the SOC design discipline, the design for yield (DFY) has the analog/mixed signal/RF unified platform. The design methodology is developed to be unified design platform for the analog/mixed signal/RF design. Based on the whole chip/board simulator, the test bench for AFE has been developed successfully. The XTALCHIP (Trademark for a chip equivalent to a crystal resonator) is the chip having the most challenging requirements of all the chips. Based on DFY design and the whole chip/board simulator, the test bench for XTALCHIP (Trademark for a chip equivalent to a crystal resonator) has been developed successfully.
Both the XTALCHIP (Trademark for a chip equivalent to a crystal resonator) and XTALCLKCHIP (Trademark for a chip equivalent to a clock chip and including means equivalent to a crystal resonator) are the trademarks of Tang System. The XTALCLKCHIP (Trademark for a chip equivalent to a clock chip and including means equivalent to a crystal resonator) is the dream to replace the Crystal on the board and clock circuits in the chip with the XTALCHIP (Trademark for a chip equivalent to a crystal resonator). Furthermore, the XTALCHIP (Trademark for a chip equivalent to a crystal resonator) can be integrated with the chip to be SOC(System On Chip). The XTALCHIP (Trademark for a chip equivalent to a crystal resonator) integrated with the clock system which comprising PLL, etc to be the XTALCLKCHIP (Trademark for a chip equivalent to a clock chip and including means equivalent to a crystal resonator). However, from the system view, the XTALCHIP (Trademark for a chip equivalent to a crystal resonator) and XTALCLKCHIP (Trademark for a chip equivalent to a clock chip and including means equivalent to a crystal resonator) have the common resources which can be shared with each other. If the XTALCLKCHIP (Trademark for a chip equivalent to a clock chip and including means equivalent to a crystal resonator) has the direct access to the interior structure of the XTALCHIP (Trademark for a chip equivalent to a crystal resonator), then the system integration will be much more realistic.
With the combination of the monolithic above-IC resonator bulk acoustic wave BAW VCO and fractional-N frequency synthesizer with randomized multiphase VCO, we have the XTALCLKCHIP (Trademark for a chip equivalent to a clock chip and including means equivalent to a crystal resonator). The XTALCLKCHIP (Trademark for a chip equivalent to a clock chip and including means equivalent to a crystal resonator) is Trimming-Free Crystal-Free Precision Reference Clock Oscillator IC chip.
Unlike the RF LC clock generator in the prior arts, the XTALCLKCHIP (Trademark for a chip equivalent to a clock chip and including means equivalent to a crystal resonator) doesn't need to trim the bandgap voltage, flat current, capacitor in the LC tank, etc. The bandgap voltage and current vary nonlinear; capacitor varies nonlinear; inductor varies nonlinear. So many nonlinear factors work and combine together, it is impossible to use the trimming to have the compensation to be constant clock frequency.
The XTALCLKCHIP (Trademark for a chip equivalent to a clock chip and including means equivalent to a crystal resonator) will generate the customer's clocks directly. So, it might consider the XTALCLKCHIP (Trademark for a chip equivalent to a clock chip and including means equivalent to a crystal resonator) without the dividers to divide the LC tank down. Instead of dividing the LC tank down, the LC tank directly converts to the customer's clocks. From the system view point, our system saves the dividing process and eliminates the noise in the dividing process. Furthermore, the customer saves the PLL. The XTALCLKCHIP (Trademark for a chip equivalent to a clock chip and including means equivalent to a crystal resonator) is to get rid of the Crystal, crystal clock circuit and the PLL circuit with the high frequency direct conversion to other frequencies without the dividing the high frequency oscillation to low frequency clock.
2. Description of Prior Art
Recently, there are some industrial activities which are what we said XTALCHIP (Trademark for a chip equivalent to a crystal resonator). They used the LC tank to generate the 1 GHz oscillation first. Then divided the 1 GHz oscillation 40 times with a series of divide-by-2 dividers. Their argument is that the phase noises will be less in the dividing process. However, this argument is not true. It violates the communication theory. In fact, the phase noise does accumulate in the dividing process. The fact is that they have to use the synchronize circuit to re-sample the divided clock 24 MHz with the 1 GHz oscillation to reduce the phase noise in the divided clock 24 MHz. Since the re-sample of the fclk with the fo oscillation of the LC tank signal, the output clock fclk must be the integer number of the fo of the LC tank. They cannot generate the customer's specified clock frequency.
Furthermore, to keep the output clock to be constant over the variation of the temperature, voltage, process and aging, they have a lot of trimming resistors, capacitors, etc in the bandgap voltage reference, current reference, LCO oscillator, etc. To calibrate the chip and have the correct trimming values to store in the on-chip NVM (Non Volatile Memory), it costs a lot of resources in the calibration and test.
They don't use the PLL circuit. Their argument is the PLL introducing a lot of phase noise to the clock. So, they don't have the capability to adjust the final clock frequency. As the LC tank does not oscillate at the specified fo, they cannot adjust the final output clock at all. Especially, they used the on-chip inductors. The L and C values of the on-chip LC tank are extremely difficult to control. It is easily out of 20% deviation from the original designed oscillation. It is impossible for them to tune the offset resonant frequency back to the original designed output clock frequency range.
Since they don't use PLL, they cannot have the fractional −N capability to meet the different output clock frequency requirement. Even if their chip can have the constant frequency fo, however, they still cannot have the different output frequency fclk for different customers.
Furthermore, the FCC requires the spread spectrum of the output clock. Since in their design, the only frequency tuner is at their LC tank to change the spread spectrum. Now, the 10 KHz variance of the 1 GHz LC tank signal, 1 G/10K=100000=17 bits accuracy. It has to use the varactor capacitance to vary with 17 bits accuracy. However, for the passive component accuracy limit is about 14 bits accuracy. So, it is impossible for the prior art which modulates the LC tank frequency to have the spread spectrum capability.
The RF LC clock generator in prior art adopts the trimming method to trim the bandgap voltage, flat current, capacitor in the LC tank, etc. However, the bandgap voltage and current vary nonlinear; capacitor varies nonlinear; inductor varies nonlinear. So many nonlinear factors work and combine together, it is impossible to use the trimming to have the compensation to be constant clock frequency.
The prior art cannot generate the custom's clock directly. The prior has to divide the oscillation LC tank down to low frequency, then the customer has to boost up the frequency to high frequency with PLL. So, even the prior art claims that they don't have the PLL, however, they push the headache and burden to the user and customer's side. For the whole system, it still has PLLs. However, the customer has to take the responsibility to develop their own PLLs to boost up the frequency to the high frequencies.
So, the prior art hides a lot true facts from the customer. It is not a practical approach at all.